1. Field of the Invention
The present invention relates to a ΔΣ (Delta Sigma) modulator and a program thereof, and particularly relates to the ΔΣ modulator for converting an m-value (m: an integer of 3 or more) digital signal into an n-value (n: an integer of 2 or more smaller than m) so as to output the converted signal, and the program thereof.
2. Description of the Related Art
Conventionally, there has been proposed a ΔΣ modulator that converts a multi-bit digital audio signal such as a PCM (Pulse Code Modulation) audio signal into a 1-bit digital audio signal or a binary digital audio signal. The ΔΣ modulator is provided with a quantizer in a feedback loop of a loop filter, and a shape of power spectrum density distribution of a quantized noise sampled at a high speed is shaped so that a dynamic range of a band pass is improved. As a result, the m-value digital signal can be encoded into an n-value digital signal of which quantization word length is smaller. Such a noise shaping operation and setting of a sufficiently high sampling frequency enable an output signal from the ΔΣ modulator to obtain a wide dynamic range at a small quantization value.
In the ΔΣ modulator, when an amplitude level of an input signal is high with respect to a corresponding quantization value of a quantizer, an operation of ΔΣ modulation signal processing occasionally becomes unstable. For example, as to the ΔΣ modulator that outputs a binary digital audio signal from a binary quantizer at a last stage, there have been considered various countermeasures such that limiters are provided to a feedback for inputting zero data or correcting an internal state of the modulator when the operation becomes unstable.
For example, conventionally, Japanese Patent No. 3142946 discloses a high order ΔΣ modulator that is stabilized regardless of an amplitude of a modulator input signal by temporarily reducing an order of the high order modulator when an amplitude of the modulator input signal exceeds an operating range of a high order modulator. Specifically, in this ΔΣ modulator, when an input signal level detected by monitoring a voltage at a stage of an integrator exceeds a stable operating range of the high order modulator, the order of a high order modulator is reduced and the modulator is temporarily converted into a first order, second order or third order modulator that is stable regardless of the input signal level. As a result, the stability is secured and return to a first integrator stage is avoided.
Further, conventionally, Japanese Patent No. 3303585 discloses a dispersive feedback ΔΣ modulator. In this modulator, a plurality of stages of integrators, each of which adds a signal obtained by delaying a self integration output by one sample to a feedback signal, described below, and inputs the added output to a limiter, and adds the output from the limiter to the integration input to obtain the integration output, is coupled in series. In the modulator, the input signal is added to a first-stage integrator, an output from a final-stage integrator is input into a quantizer, an output signal from the quantizer is delayed by one sample and is multiplied by a suitable coefficient, and the multiplied signal is used as a feedback signal of each integrator.
Further, conventionally, as the invention in which, when a digital signal expressed by 1 bit is subject to predetermined signal processing and a digitally processed signal of which signal amplitude exceeds 1 bit is input and predetermined ΔΣ modulation processing is executed on the digitally processed signal, the processing is executed so that an amplitude of an output signal is expressed by 1 bit, Japanese Patent No. 4214850 discloses a digital signal processing apparatus. This digital signal processing apparatus includes a second or higher order first ΔΣ modulating unit having a first quantizing unit having a quantization amplitude value for enabling a signal amplitude of the processed digital signal input and quantized into at least n bit (n: an integer of 2 or more), and a second or lower order second ΔΣ modulating unit having a second quantizing unit having a quantization amplitude value for making a modulation signal output from the first ΔΣ modulating unit equal to the signal amplitude value of the digital signal.
The present invention is devised in order to easily solve the problem that shared in common with the above conventional technique, and its object is to provide a ΔΣ modulator in which an operation of ΔΣ modulation signal processing is stable even when a quantization value of an m-value digital signal input is larger than a quantization value of an n-value digital signal output and an amplitude level of an input signal input into a quantizer is comparatively large.